lllllllllllllllllllApril 22, 2024

Design Verification Engineer

  • IT Services & Consulting
  • Full Time, Permanent
  • 1 month ago
  • Mumbai

Job Information

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    Salary Rupees 25-35 Lacs / Yearly
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    Shift Morning
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    No. of Openings 15 openings
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    Job Level : Officer
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    Job Experience : 6 - 10 years
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    Job Qualifications Bachelor

Job Description

Role & responsibilities

Bachelors or master is required.
• 6 to 9 of experience in Digital ASIC/FPGA verification.
• Experience in identifying, tracking, and providing status of technical performance metrics to
measure progress and ensure compliance with requirements.
• In depth experience in writing Universal Verification Methodology (UVM) sequences and virtual sequences and its concepts like Inheritance, Polymorphism, etc.
• Experience in using Universal Verification Methodology (UVM): Experience creating drivers, monitors, predictors, and scoreboards.
• Experience working with self-checking simulation test bench from scratch for SoCs/ASIC/FPGA.
• Experience in verification working with internal/external VIPs, its development and evaluation with multiple vendors.
• In depth understanding in System Verilog language and verification concepts.
• Work experience using Linux or Unix terminal commands.
• Experience using scripting languages: Make, Perl, Python, shell scripts, etc.
• Experience using Revision Control Systems: Subversion (SVN), CVS, Git.

Preferred Qualifications (Desired Skills/Experience):

  • Good Understanding upon designing digital ASIC/FPGA architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
    • Experience in Avionics protocols is a plus

Typical Education & Experience:
Bachelor / Master / Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry with 6 to 9 years of experience & Master’s degree with 5+ years of experience

Preferred candidate profile

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